I was reading an article about the cost of a transaction and how many MIPS (Millions of Instructions Per Second) it used.  This annoyed me as it is wrong at so many levels.

1. MIPS depends on how long the transaction ran for. Millions of Instructions used (MINU?) would be a better metric
2. Instructions are different sizes, and the CPU used by an instruction varies depending on many things.
3. If I was to talk about “How many fruit I can get per kilogram”, you would rightly say that  apples weigh more than grapes. You get different sorts of apples of different sizes, so you might get 12 cox’s apples per kilogram, but 10 Granny Smiths.  I’m sure you are thinking number of fruit per kilogram is a stupid measurement.   I agree – but this is the same discussion as MIPS.

1. Obvious statement : The duration of an instruction depends on the instruction.   Instructions that access memory are often slower than instructions that just access registers.
2. Not so obvious statement.    The same instruction (for example load register) can have different durations
3. Not at all obvious:  The same physical instruction – for example in a loop – can have different durations
4. Not at all obvious: A register to register instruction can be slower than a memory to register instruction.

Let’s take the covers off and get our hands under the covers.

1. The z machines have the processors in “books”; in reality these are big cards.
2. There can be multiple chips per book.
3. There is memory in each book
4. The length of the wire between two books might be 1 metre.
5. Inside each chip are the processors.
6. Each processor has cache for instructions, and cache for data.  This memory is within a few millimetres of the processors
7. There is cache on the chip independent of the processors, it is within 1 cm of the processors.

Just a few more observations

1. The Load instruction – is not an instruction – it is actually a microprogram using the underlying chip technology
2. Some instructions were written in millicode – and then a release or so later were written in microcode.   The MVCL instruction is a good example of this.  It can move Megabytes of data in one instruction.

For the instruction L R4,20(R3).   This says load register 4 with the contents of  20 bytes off what register 3 point to.   I’ll look at how long this instruction takes to execute.

Put this load instruction in a little loop and go round the loop twice.

JUMPHERE SR    R1,R1    clear register 1
LOOP     LTR   R1,R1    test register 1
         BNZ   PAST    If it is non zero go to PAST
         L     R4,20(R3) Load register 4 from storage  
         AFI   R1,1     Add 1 to register 1
         B     LOOP     
PAST     DS   0H   

What are the differences in the duration of the L R4,20(R3) instruction, first time and second time around the loop?

1. If the application issued goto/jump to JUMPHERE, this block of code may not be in the processor’s instruction cache.  It may be in the chips’ cache.  If so – there will be a delay while the block of instructions are loaded into the proccessor’s cache.
2. When the Load instruction is executed – both times it is in the processor’s cache, so there is no time difference.
3. The first time, the instruction has to be parsed into  “Load”, “register 4″,”20 bytes from what register 3 points to”.   The second time, it can reuse this information – so it will be quicker.
4. “Go and access the storage from what register 3 points to”.  You have convert register 3 to a real page. There are lots of calculations to Translate a virtual address to its “real address”.  For example each address space has an address 2000. It needs to use the look up tables for that address space to map 2000 to the real page.  Once it has calculated the “real” page – it keeps it in a Translation Lookaside Buffer (TLB). (LPAR#.ASID#.2000 -> 39945000).   The second time, this information is already in the TLB.
5.  The “real” storage may be in the same chip as you are executing, or it may be on a different chip.  It could be on a chip on a different book.  There is about 1 meter of cabling between where the real storage is, and the instruction requesting it.  The speed of light determines how long it will take to access the data – 0.000001 of a meter or 1 meter.    The second time the load instruction is executed, it is already in the processors’ cache.

In this contrived example I would expect the second load to be much faster than the first load – perhaps 1000 times faster.  Apples and grapes…

The z Hardware can report where time is being spent, and allows IBM to tune the programs to reduced delays.

There was one z/OS product which had a pointer to the next free buffer in the trace table.   The code would get the buffer and update the pointer to the next free buffer.  This worked fine when there was only one thread running.  On a big box with 16 engines every processor was trying to grab and update this pointer.   Sometime it had to grab it from a different book, sometimes it had to grab it from another processor in the same chip.  From the hardware instrumentation it was obvious that a lot of time was spent waiting for this “latch”.   By giving each processor its own trace table – totally removed this contention, and the trace buffers were close to the processors – so a win win situation.

I said that a register to register could be slower than a memory to register – how?

The processors can process multiple instructions in parallel.  While it is waiting for some storage to arrive from 1 metre away, it can be decoding the next 10 instructions.  There is what I like to think of as a “commit” in all processing, and the commit processing has to be done in strict order. 

So if we had

    L  R1,20(R3)      
    SR  R4,R4
    SR  R6,R6  

The two Subtract Registers may be very quick and almost completed before the Load instruction has finished. They cannot “commit” until the Load has committed.   Picture trying to debug this if the instructions had been executed out of order!

Now consider

 L    R1,20(R3)      
 LTR  R1,R1  Test if register 1 is zero 
 LH   R6,100(R7) 
 

The Load and Test Register(LTR) is using register 1 – which is being used by the Load instruction.  The LTR has to wait until  the previous Load has “Committed” before it can access the register.  In effect the LTR is having to wait until the Load’s data is retrieved from 1 metre away – so very slow.

The data for the Load Halfword R6,100(R7) may be in the data cache – and so be very fast.   We therefore have the situation that the register, register instruction LTR takes a “long” time, and the memory register Load Halfword – is blazingly fast.

Things ain’t what they used to be.

I remember when IBM changed from Silicon processors to CMOS.  We went from a machine with one engine delivering 50 MIPS to a machine with 5 processors each delivering 11 MIPS.   The bean counters said “be happy – you have more MIPS”.    The transactions were now 5 times slower, but you could now have 5 transactions  running in parallel, and so overall throughput was very similar.  I wonder if these bean counters are the ones who think that if the average family has 2.5 children, there must be a lot of half brothers and half sisters.

For those people who have to compare one box with another box, or want to know how much CPU is needed for a transaction use CPU seconds.  There are tables giving a benchmark of the same workload on different machines, and so you can make comparisons between the machines.

I found there were many reasons why a browser’s or curl application’s digital certificate did not work with MQWEB, from an option missing, to unsupported handshake option.  Often there the messages were the vague “A problem has occurred”.

I tried to cause as many problems as possible, and blogged what you get, and the resolution; but event then I found there were even more ways of it failing.

I’ve written some java programs called checkTLS which act as a client or a server.

• You can use your web browser into the server application and see information about what is being used, and if it can detect any problems (such as expired CA)
• You can extract your certificates from the browser, and then talk to MQWEB, and see what happens in the handshake

This is alpha code.   I would be interested in any comments

• Is this useful?
• Does it work for you?
• Is it too verbose?

I was trying to get my Linux machine talking to MQWeb browser on z/OS, but I was getting

curl .. Failed to connect to 10.1.1.2 port 9443: Connection refused.

For this to work you have to edit the mqwebuser.xml file and uncomment

<variable name="httpHost" value="*"/> 
<!-- 
-->

It then worked a treat.  Like most things it is easy when you know how to fix it.

Using firefox browser then gave me

Web sites prove their identity via certificates. Firefox does not trust this site because it uses a certificate that is not valid for 10.1.1.2:9443.
Error code: MOZILLA_PKIX_ERROR_SELF_SIGNED_CERT

Which proves I was accessing the site. That is a certificate set up issue, and a whole different ball game.

If you are using the mqweb browser on z/OS, there is a configuration file.

It looks (by using the ls -T command) to be in ASCII format (ISO8599-1), so oedit … does not work.

Try using ISPF 3.17 z/OS Unix Directory list.

I was investigating purchasing something expensive like a car, and found a web site which was hard to read.  The long forgotten words of my English teacher from over 50 years ago came into my mind.

For a well written document,

1. every sentence should be read just once
2. it should be easy for the reader

For example words on a web page for selling a new car

1. The Supervandex model-95 has twin cam, 16 valve supercharged petrol engine with a vanadium gismo, has a 16 speaker all round system.  It has 2 seats and enough space for some small suitcases, and looks really cool.
2. The Supervandex model-96 has single cam, 8 valve supercharged petrol engine with a vanadium gismo, has a 8 speaker all round system.  It has 4 seats and enough space for some small suitcases, a dog and a set of golf clubs.  This is a practical car.

What is wrong with those statements?

For the car sales person this is very clear as he or she needs to know the details of each model.  For the average punter like me, who wants a petrol car  with space for 2 dogs and my mother’s walking frame; the sentences are hard to read and require a lot of work. My thoughts would be

1. “Supervandex-95 … blah blah Petrol – that’s good’… what model ? (reread the sentence) the Supervandex-95 blah blah blah… 2 seats – that’s no good for me”
2. “Supervandex-96 … blah blah Petrol – that’s good’… what model ? (reread the sentence) the Supervandex-96 blah blah blah… 4 seats – and it looks like a big enough boot.  Supervandex 96 sounds like the one I need”

I had to read parts of each sentence more than once, and had to keep information in my short term memory, and then forget it when it was no longer needed.

For someone wanting to buy a car (and did not care what the model number was), I think the following would be clearer.

1. The two seater petrol car with space for a couple of suitcases (The Supervandex-95) has twin cam, 16 valve supercharged petrol engine with a vanadium gismo, has a 16 speaker all round system.
2. The four seater petrol car  with enough space for some small suitcases, a dog and a set of golf clubs (the Supervandex-96) has single cam, 8 valve supercharged petrol engine with a vanadium gismo, has a 8 speaker all round system.

Now, my thoughts are

1. “Two seater… not big enough I’ll skip the rest of the sentence and go to the next item
2. “Four seater, and enough space in the boot, this looks interesting.   The Supervandex-96… boring boring boring.   So it is the Supervandex 96 for me”

I did not have to read the whole of the first sentence, and from the second sentence I could quickly see that it met my requirements.  I only had to remember Supervandex-96.

For me the second text was better than the first text.

There is the automated readability index = 4.71 *( number of characters/number of words) + 0.5* (number of words/number of sentences) – 21.43.  A score of 1 is for kindergarten, a score of 14+ is Professors.

We could have the PEE test – the Paice’s Eyeball Energy test – compare texts by monitoring the movement of the eyeball, and work out the energy in micro-joules for each text. Every time the eye had to go back it would take energy to stop the eyeball, go back, and reread the text.  ( Of course you would have to have a standard eyeball mass, and the text read from a fixed distance, so the energy to move the eyeball is the same – nothing insurmountable.)

We could take this further and take an electroencephalogram (EEG – a swimming cap with lots of electrodes detecting brain activity), and see how much electrical activity was generated when trying to parse statements.   I remember being in China, when someone from the UK was trying to explain something to the Chinese managers (who could understand English – but not speak it), using one very long statement; many ifs, and whethers, and depending ons.  My short term memory overflowed, and I was writing down what the person was saying.    The amount of electrical energy I used to parse and process the nested conditional text would have powered a light bulb!  I pitied the poor Chinese who ignored the statement and then said “thank you, our next question is …”. 

I had a mentor who said before you send an email or go into a meeting, ask yourself “why are you telling your audience this information?” is it

1. just for information
2. for action
3. it is such good news – Ive got to tell every one

then in the meeting tell them “I am telling you this because … you need to take an action”, or “for information”.    If it is for information only, then they can only half listen.  If they need to take action, for example spend money, they will give it their full attention.

Why am I telling you about the PEE test?

When you write emails of documents you need to understand who your audience is, and what they want out of the information. People should be able to read the information without going back and rereading it.

Am I going to buy the Supervandex-96 model ?  I don’t know  – they only gave the price of the Supervandex-95 model. This goes to show a low PEE value is not the perfect solution.